



The DSP Starter kit consists of TMS320C6711 Floating Point Digital Signal Processor and a 16 bit dual-channel voice/data codec TLC320AD535 for input/output support. This codec uses Sigma-Delta Technology for Analog to Digital/Digital to Analog conversion. This codec has a fixed sampling rate of 8 KHz. The DSP uses Very Long Instruction Word (VLIW) Architecture. There are many ways of generating PWM signals. The ADC converts an input signal into discrete output digital words in 2’scomplement format that correspond to the analog signal value
Polling Method
The Multichannel Buffered Serial Port (McBSP) can be interrupt driven or can be driven by polling method. A polling-based program (non-interrupt driven) continuously polls or tests whether or not data are ready to be received or transmitted. This scheme is less efficient than the interrupt scheme. Within the output write function mcbsp0_write, SPCR is ANDed with 0x20000 to test bit 17 .
temp = *(unsigned volatile int *)McBSP0_SPCR & 0x20000;
An output data value is sent through the data transmit register of McBSP. The polling technique uses a continuous procedure of testing when the data are ready.
The following lines of code are used to generate a PWM wave
comm_poll();
while(1)
{
y=-ampoframp*ramp1000[i];
i = (i + freqoframp) % 2000; //next sample is + freq in table
x=ampofsine*sine8000[j];
j = (j + freqofsine) % 8000; //next sample is + freq in table
if (y < x)
pwm=-10000;
else pwm=10000;
output_sample(pwm);
}
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